Design Principles and Selection Considerations for Fractional Frequencies in Crystal Oscillators

In hardware clock system design, engineers often encounter seemingly “irregular” crystal oscillator frequencies such as 11.0592 MHz, 3.579545 MHz, and 19.6608 MHz. These fractional frequency points are not chosen arbitrarily; they are the inevitable result of communication protocols, division constraints, and systemlevel reverse requirements. This article starts from the underlying principles, analyzes the logic behind fractional frequency generation, and provides practical screening methods for selection.

1. Core Design Logic of Fractional Frequencies

As the system clock source, the crystal oscillator’s frequency is always chosen to serve the precise timing requirements of downstream digital circuits (PLLs, dividers, serial communication, etc.). Fractional frequencies mainly arise from the following four types of design constraints:

1.1 Matching Integer Division for UART – Achieving ErrorFree Baud Rates

The serial baud rate is obtained by dividing the system clock by an integer divisor, according to the formula:

Baud Rate = Clock Frequency / Division Factor

To accurately generate standard baud rates (e.g., 9600, 19200, 115200 bps), the division must be exact. Take 1.8432 MHz as an example – with 16× oversampling:

1.8432 MHz ÷ 16 = 115.2 kHz, i.e., 115200 bps.

Similarly, 11.0592 MHz and 19.6608 MHz are respectively 6 and 10.666… times 1.8432 MHz (11.0592 = 1.8432 × 6; 19.6608 = 1.8432 × 10.666…, often achieved with a PLL). However, these frequencies are more commonly used directly as the main clock for MCUs (like 8051), allowing the internal UART divider to produce all standard baud rates exactly. If an integer frequency such as 20 MHz is chosen, it cannot divide evenly to produce 115200, leading to cumulative errors, frame errors, or packet loss.

1.2 Fitting a Binary DividebyTwo Architecture – Simplifying Clock Tree Design

Frequencies such as 20.48 MHz, 10.24 MHz, 5.12 MHz can be expressed as 2ⁿ × 10 kHz (e.g., 20.48 MHz = 2048 × 10 kHz). After cascaded dividebytwo stages, such frequencies generate subclock domains like 10.24 MHz, 5.12 MHz, 2.56 MHz, 1.28 MHz, etc. This architecture is ideally suited for binary counters or shift registers, resulting in a simple circuit structure, deterministic phase relationships among divided clocks, and consistent timing margins. These frequencies are common in industrial DSPs, PLCs, and servo drives.

1.3 Synthesized via PLL – Meeting HighSpeed Communication and Audio/Video Sampling Standards

Modern SoCs, optical modules, and video processors incorporate PLLs. They typically use a standard integer reference frequency (e.g., 25 MHz, 24 MHz) and then generate specific nonstandard frequencies through integer or fractional division/multiplication. Typical examples include:

74.25 MHz – SMPTE standard highdefinition video sampling clock for formats like 1080i/720p.

33.1776 MHz – commonly used in audio Codecs and wideband RF frontends; through a PLL, it can accurately produce the 44.1 kHz or 48 kHz audio sampling rate families.

25.000625 MHz – some Ethernet PHYs use this with a fractional PLL to generate a precise 125 MHz serial data rate for 1 Gbps line rate (note: 25 MHz integer multiples are more common in practice; this is just an example).

It should be noted that fractional division introduces deterministic jitter and spurs. For phasenoisesensitive applications, it is preferable to choose a target frequency that can be obtained by integer division, or to use a lownoise PLL with appropriate loop bandwidth settings.

1.4 Following IndustryStandard Historical Protocols and EMC Considerations

Fixed historical protocols: USB 2.0 specifies a 48 MHz highspeed clock; Ethernet MACs use 25 MHz / 125 MHz; realtime clocks (RTC) use 32.768 kHz (2¹⁵ Hz). These frequencies were fixed when the standards were established and have been adopted across the entire supply chain, becoming defacto standards.

Electromagnetic compatibility (EMC): The highorder harmonics of integer frequencies may overlap with power supply, RF, or wireless communication bands, causing interference. Selecting a local oscillator frequency with a fractional part can spread or shift harmonic energy, reducing EMI risk and lowering filtering and shielding costs.

2. Other Critical Factors in Crystal Oscillator Selection

Beyond the frequency value, the following engineering considerations are equally important:

Phase Noise and Jitter
Although a PLL can synthesize arbitrary frequencies, fractional division significantly degrades closein phase noise and random jitter. For highspeed optical modules, millimeterwave radar, or 5G fronthaul applications, it is recommended to directly choose a native crystal oscillator frequency that meets the phase noise specifications, avoiding insufficient signalintegrity margin later.

Lead Time and Cost
Nonstandard or custom frequencies often require long lead times and high NRE (nonrecurring engineering) fees. Within acceptable performance limits, priority should be given to industrystandard mainstream frequencies (such as common integer frequencies like 25 MHz, 27 MHz, 40 MHz, 50 MHz, as well as the standard fractional frequencies mentioned above) to shorten development cycles and control BOM costs.

Domestic Replacement Compatibility
Domestic quartz crystal manufacturers now cover the vast majority of commonly used integer and fractional standard frequencies. When selecting, pay attention to supply stability, temperature characteristics (e.g., ±10 ppm, ±20 ppm), and load capacitance parameters to ensure compatibility with the main chip’s clock input requirements.

3. Practical Screening Recommendations

Determine system clock constraints: list all precise clock frequencies required by peripheral interfaces (UART, I2S, SPI, Ethernet, USB, Video) and their tolerance.

Derive the required crystal reference frequency: if the main chip has an internal PLL, choose a reference crystal that can generate the target frequencies via integer division ratios or lowfractional division ratios. Prefer ratios with a denominator that is a power of two and a division ratio less than 100.

Verify division error: calculate whether the division error is within the maximum allowable baud rate / sampling rate deviation for each peripheral (typically < ±2%).

Assess EMI risk: perform a spectral estimation of highorder harmonics; if necessary, choose a frequency that avoids integermultiple harmonics.

Balance supply and cost: under the premise of meeting performance, select models that are readily available in the market, with package types (e.g., HC49S, SMD 3.2×2.5 mm) that suit production requirements.